1. Field of the Invention
The present invention relates to a semiconductor device that includes a low dielectric constant film.
2. Description of the Background Art
With progresses in the miniaturization of semiconductor devices, the parasitic capacitance of copper wires has become approximately the same as the input/output capacitance of transistors, preventing increase in the speed of the device operation. Therefore, ways to introduce an insulating film, of which the relative dielectric constant is lower than that of a conventional silicon oxide (SiO2, specific dielectric constant k≈4), have been actively sought. When relative dielectric constant k becomes small, however, the physical strength of an insulating film becomes inferior. In particular, when relative dielectric constant k becomes smaller than 3.5, sufficient physical strength cannot be maintained, leading to a problem. In the following, a film of which relative dielectric constant k is smaller than 3.5 is referred to as “low dielectric constant film,” in the present invention.
During heat cycle testing, after semiconductor devices have been packaged, temperature is changed, for example, from −65° C. to 150° C., and therefore, low dielectric constant films receive stress from resin portions, and as a result, in some cases, the low dielectric constant films peel. The lower the physical strength of a low dielectric constant film, the more significant peeling becomes. In addition, as for the location of peeling, it is particularly significant in the vicinity of chip corners, where stress concentrates.
In general, when moisture enters into the inside of a chip of a semiconductor device, the operation properties of the device deteriorate, and for this reason, a pattern that is referred to as a seal ring (also referred to as “guard ring”) is formed, in order to prevent entering of moisture from sides on the outer periphery of the chip. The seal ring is arranged in closed loop form in a plan view, where metal portions, such as contacts and wires that are used within the chip, are aligned in the upward and downward direction, and these layers are connected to each other through a structure in trench form that is also made of metal, so that a metal wall is formed. In a plan view, the seal ring becomes rectangular, with an outer periphery that is constantly spaced from the outer periphery of the chip.
When a low dielectric constant film is destroyed due to stress that is received from resin, as described above, cracking eventually progresses and reaches the seal ring. When cracking reaches the seal ring, the seal ring is easily destroyed. Once the seal ring is destroyed, moisture enters into the inside of the chip, causing a failure in the operation of the device. Furthermore, in extreme cases, cracking may progress as much as 500 μm and, in some cases, directly cut wires inside the chip.
In order to prevent destruction of the seal ring by cracking, several technologies have been proposed. U.S. Pat. No. 6,365,958, for example, discloses an arrangement of a member having a structure where a number of layers of lattice wires are arranged so as to overlap in the upward and downward direction, and lattice wires which are on top of one another are connected by means of vias that are made of metal outside of the seal ring as a sacrifice pattern for stopping the progress of cracking. U.S. Pat. No. 5,572,067 discloses an arrangement of a sacrifice corner structure where a lower layer wire that is parallel to the direction toward the center from the corner of the chip and an upper layer wire that is oriented perpendicular to this cross each other and are connected to each other by means of a via in a chip corner portion. U.S. Patent Publication No. 2004/0002198 discloses the placement of dummy metal patterns where a non-quadrilateral seal ring is used and placed in a corner portion of the chip, where a lower layer wire and an upper layer wire are connected in lattice form on both sides of the seal ring.
Japanese Patent Laying-Open No. 2004-172169 discloses a reinforcing pattern where a lower layer wire and an upper layer wire are connected through a via and an arrangement of a reinforcing pattern in wall form made of copper in the vicinity of a chip corner.
Even in the case where a structure that becomes a sacrifice pattern is arranged in the vicinity of a chip corner in accordance with a proposed technology, such as those that have been as described above, destruction of the seal ring by cracking cannot be sufficiently prevented. In addition, when the sacrifice pattern is made too great, a problem arises where the area on which circuits or the like are arranged becomes too small.